In some approaches related to a memory array with a multiplexing scheme, power wastage may result. For illustration, the memory array is configured as a multiplexing of 8, in which eight pairs of bit lines of eight corresponding memory cells are coupled to a multiplexer. In a read operation, one memory cell is read, the other seven memory cells are not read, but eight pairs of bit lines are pre-charged to a high logical value. All eight memory cells then discharge the high logical value of their corresponding bit lines. Discharging the bit lines of the seven memory cells that are not read results in power wastage.
Like reference symbols in the various drawings indicate like elements.